1. Field of the Invention
This invention relates to an improved TTL to CMOS buffer, and central bias generator therefor.
2. Prior Art
Ratioed CMOS inverters are commonly used in industry for realizing a TTL to CMOS buffer. The problem is to achieve the ideal switch point of 1.4 volts, but the NFET to PFET conductivity ratio is 16 or greater. The higher the ratio, the lower the power supply sensitivity and the greater the switch point dependency on NFET threshold. By way of example, for a conductivity ratio of 16, the power supply sensitivity of the switch point is 0.2 volts/volt, while the switch point dependency on the PFET threshold is 0.2.times.V.sub.tp and on the NFET is 0.8.times.V.sub.tn. Since the square root of the conductivity ratio has almost no dependence on temperature, the factor that has the biggest impact on the temperature coefficient of the switch point is the NFET threshold voltage.
Further, radiation hard processes usually have a higher V.sub.tn which is an added complication in designing a TTL buffer. In certain SOS processes, the threshold voltage at room temperature is 1.2+ or -0.2 volts. Over the Mil temperature range, the V.sub.tn can be as high as 1.53 volts, making it impossible for the switch point to approach the ideal value of 1.4 volts no matter what NFET to PFET conductivity ratio is used.